1. Field of the Invention
This invention concerns the control unit which is used for the control of the common memory of an ATM node, whereby the ATM-node is connected to a first plurality of incoming lines and to a second plurality of outgoing lines. The ATM-node serves for the continuous reception and onward routing of address-labelled cells with uniform length and uniform construction, which cells arrive or leave over the lines, and to which cells a number of distinguishable priorities are associated. The common memory serves for the intermediate storage of all cells which should be sent out on one of the outgoing lines. Additionally, the common memory has a third plurality of storage blocks, which are individually selectable by addresses and each of which serves respectively for the reception of a cell. The control unit comprises means for management and control as well as a sequencer, with whose help the storage blocks of the common memory are managed and the sequential reading in and reading out of cells, respectively into or out of the storage blocks is controlled. It further concerns the method of operation of the node.
The term ATM (Asynchronous Transfer Mode) is known for a technique for broadband communication in the region of about 155 to 622 Mbit/s and much more. The technique is considered as a type of packet switching, in which all the packets are address-labelled and have a uniform length. Hereafter, these packets are termed "cells" in conformance with other literature.
ATM nodes serve to route cells to the required destination as is generally described by means of FIG. 1, later.
2. Description of Prior Art
ATM nodes can be constructed in many different ways. The type which employ a common memory in accordance with the patent BE 904 100, seem to be particularly advantageous since, with this technique, the problem of the blocking of one of the output links, or even the whole node can be easily overcome.
One of this type of ATM node is known in detail from the document EP-A-299 473. This node has a main memory, via which all cells are sent out, an address-pointer store for the management of the addresses in the main memory and a third store for the management of the empty entries in the main memory (the idle address FIFO). The address-pointer store comprises primarily a whole series of registers. These registers are associated uniquely with the outgoing lines. They serve, respectively, for the storage of the addresses of the storage blocks in the main memory in which are stored either the cells which must be sent out next on the respective associated outgoing line, or into which the next arriving cells should be stored. The information about how many cells are stored, and in which storage blocks, is associated with the respective cells and stored with them in the main memory. Therefore, direct access cannot be made to this information.
A further document EP-A-336 373 from the same applicant, describes a very similar ATM node, in which the emphasis is placed on a so-called multicast facility, ie. the possibility for certain cells to be sent not only respectively to just one single address, but to any number of freely selectable addresses.
The structure of the known ATM node is such that the real storage function of the main memory is combined with the logic and control functions for locating where cells are to be stored into, or read out from. This is a substantial handicap, that manifests itself in the form of logic which is difficult to understand and is inflexible. In particular, this structure necessitates the use of VLSI (Very Large Scale Integration)--or custom-chips, which require a considerable amount of development effort.